1. Field of Invention
The present invention relates to a type of electrostatic discharge (ESD) protection device and its manufacturing method. More particularly, the present invention relates to a type of electrostatic discharge protection device and associated manufacturing method that uses a self-aligned silicide (Salicide) process, and is capable of preventing burnout of the drain terminal due to overheating.
2. Description of Related Art
In the manufacturing of electrostatic discharge protection devices that use a self-aligned silicide (Salicide) process, there are two salicide block layout designs. The purpose of the block layout designs is to avoid the formation of a silicide layer over the drain terminal. The first design is to block the drain terminal only, and the second design is to block the drain terminal, the source terminal as well as the gate terminal. Both designs are described in detail below.
FIGS. 1A through 1D are a series of cross-sectional views showing the progression of steps in the manufacturing of a conventional electrostatic discharge protection device that uses a self-aligned silicide process and employing a first block design. First, as shown in FIG. 1A, a semiconductor substrate 10 that has a gate 11, a source region 12, a drain region 13, already formed thereon is provided. Then, a cap oxide layer 14 is formed over the gate 11, the source region 12 and the drain region 13. The cap oxide layer 14 can be, for example, an undoped silicon dioxide (SiO.sub.2) layer, and preferably an oxide layer deposited using a plasma-enhanced chemical vapor deposition (PECVD) method with silane (SiH.sub.4) or tetraethyl orthosilicate (TEOS) as the base material. Next, as shown in FIG. 1B, a photoresist layer 15 is formed over the cap oxide layer 14 using photolithographic processes. Thereafter, as shown in FIG. 1C, the cap oxide layer 14 is etched using the photoresist layer 15 as a mask to expose the gate 11, the source region 12 and a portion of the drain region 13. Finally, as shown in FIG. 1D, a self-aligned silicide processing operation is performed to form a silicide layer 16 above the exposed gate 11, the source region 12 and a portion of the drain region 13. It is obvious from the above method that a portion of the drain region 13 is covered by a silicide layer 16 in the final structure.
FIG. 2A through 2C are a series of cross-sectional views showing the progression of steps in the manufacturing of a conventional electrostatic discharge protection device that uses a self-aligned silicide process and employing a second block design. First, as shown in FIG. 2A, a semiconductor substrate 20 that has a gate 21, a source region 22, a drain region 23, a field oxide layer 24, already formed thereon is provided. Then, a cap oxide layer 25, for example, an undoped silicon dioxide (SiO.sub.2) is formed over the substrate 20. Next, as shown in FIG. 2B, a photoresist layer 26 is formed over the cap oxide layer 25 using photolithographic processes. Next, as shown in FIG. 2C, the cap oxide layer 25 is etched to leave a residual cap oxide layer 25 above the gate 21, the source region 22 and the drain region 23 using the photoresist layer 26 as a mask. Thereafter, subsequent self-aligned silicide processing operation is performed.
A number of defects can be found for the above two self-aligned silicide block layout designs. For the first block layout design shown in FIG. 1A through 1D, the cap oxide layer only blocks a portion of the drain terminal. When a self-aligned silicide processing operation is performed, a silicide layer can still be formed in the area above the drain region neighboring the gate terminal. Therefore, whenever a large stress voltage is applied to the drain terminal, a large conducting current will flow through due to the presence of a low resistant silicide layer above the drain terminal. The passing of a large current through the drain terminal next to the gate generates a lot of heat that may result in the burnout of drain terminal. This can cause the malfunctioning of the electrostatic discharge protection device. On the other hand, for the second block layout design shown in FIG. 2A through 2C, the cap oxide layer blocks the gate, the source and the drain terminal entirely. Due to the presence of an oxide layer over the gate and the source terminal, a silicide layer is difficult to establish itself thereon. This may lead to a high gate and source terminal resistance. A high gate and source terminal resistance can affect the input and output timing characteristic of a circuit.
In light of the foregoing, there is a need in the art for an improved method for producing electrostatic discharge protection devices.